HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 455
HD64F2623FA20J
Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2623FA20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Note:
Bit 4—Parity Mode (O/E E E E ): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,
when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor
format is used.
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the
STOP bit setting is invalid since stop bits are not added.
Bit 5
PE
0
1
Bit 4
O/E E E E
0
1
Bit 3
STOP
0
1
* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
2. When odd parity is set, parity bit addition is performed in transmission so that the total
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
Description
1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end
2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit
of a transmit character before it is sent.
character before it is sent.
2
1
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 429 of 1042
REJ09B0275-0500
(Initial value)
(Initial value)
(Initial value)
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