HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 153

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.1
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1
The PC break controller has the following features:
Two break channels (A and B)
The following can be set as break compare conditions:
The timing of PC break exception handling after the occurrence of a break condition is as
follows:
Module stop mode can be set
24 address bits
Bit masking possible
Bus cycle
Instruction fetch
Data access: data read, data write, data read/write
Bus master
Either CPU or CPU/DTC can be selected
Immediately before execution of the instruction fetched at the set address (instruction
fetch)
Immediately after execution of the instruction that accesses data at the set address (data
access)
The initial setting is for PBC operation to be halted. Register access is enabled by clearing
module stop mode.
Features
Overview
Section 6 PC Break Controller (PBC)
Rev. 5.00 Jan 10, 2006 page 127 of 1042
Section 6 PC Break Controller (PBC)
REJ09B0275-0500