HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 265

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Port A Data Direction Register (PADDR)
Note:
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
Port A Data Register (PADR)
Note:
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA5DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
* In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
* In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
read.
:
:
:
:
Undefined Undefined
Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
PA5DDR * PA4DDR * PA3DDR
PA5DR * PA4DR * PA3DR
R/W
W
5
0
5
0
R/W
W
4
0
4
0
Rev. 5.00 Jan 10, 2006 page 239 of 1042
R/W
W
3
0
3
0
PA2DDR
PA2DR
R/W
W
2
0
2
0
Section 9 I/O Ports
PA1DDR
PA1DR
REJ09B0275-0500
R/W
W
1
0
1
0
PA0DDR
PA0DR
R/W
W
0
0
0
0