HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 19

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3 Operation .......................................................................................................................... 412
12.4 Interrupts ........................................................................................................................... 417
12.5 Usage Notes ...................................................................................................................... 417
Section 13 Serial Communication Interface (SCI)
13.1 Overview........................................................................................................................... 421
13.2 Register Descriptions ........................................................................................................ 426
13.3 Operation .......................................................................................................................... 450
13.4 SCI Interrupts.................................................................................................................... 480
13.5 Usage Notes ...................................................................................................................... 482
Section 14 Smart Card Interface
14.1 Overview........................................................................................................................... 491
12.3.1 Watchdog Timer Operation ................................................................................. 412
12.3.2 Interval Timer Operation ..................................................................................... 415
12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 415
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 416
12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 417
12.5.2 Changing Value of PSS and CKS2 to CKS0 ....................................................... 418
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 418
12.5.4 System Reset by WDTOVF Signal...................................................................... 418
12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 418
12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 419
13.1.1 Features................................................................................................................ 421
13.1.2 Block Diagram ..................................................................................................... 423
13.1.3 Pin Configuration................................................................................................. 424
13.1.4 Register Configuration......................................................................................... 425
13.2.1 Receive Shift Register (RSR) .............................................................................. 426
13.2.2 Receive Data Register (RDR) .............................................................................. 426
13.2.3 Transmit Shift Register (TSR) ............................................................................. 427
13.2.4 Transmit Data Register (TDR)............................................................................. 427
13.2.5 Serial Mode Register (SMR)................................................................................ 428
13.2.6 Serial Control Register (SCR).............................................................................. 431
13.2.7 Serial Status Register (SSR) ................................................................................ 435
13.2.8 Bit Rate Register (BRR) ...................................................................................... 439
13.2.9 Smart Card Mode Register (SCMR) .................................................................... 447
13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 448
13.3.1 Overview.............................................................................................................. 450
13.3.2 Operation in Asynchronous Mode ....................................................................... 452
13.3.3 Multiprocessor Communication Function............................................................ 463
13.3.4 Operation in Clocked Synchronous Mode ........................................................... 471
..................................................................................... 491
Rev. 5.00 Jan 10, 2006 page xvii of xxiv
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