HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 619

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.2
16.2.1
Bit
Initial value
R/W
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in
table 16.3.
ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower
byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3,
Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 16.3 Analog Input Channels and Corresponding ADDR Registers
Group 0
AN0
AN1
AN2
AN3
Channel Set 0 (CH3 = 0)
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
:
:
:
AD9
Group 1
AN4
AN5
AN6
AN7
15
R
0
AD8
14
Analog Input Channel
R
0
AD7
13
R
0
AD6
12
R
0
Group 0
AN8
AN9
AN10
AN11
AD5
11
R
0
Channel Set 1 (CH3 = 1)
AD4
10
R
0
AD3
R
9
0
Group 1
AN12
AN13
AN14
AN15
AD2
R
8
0
Rev. 5.00 Jan 10, 2006 page 593 of 1042
AD1
R
7
0
AD0
R
6
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
—
R
5
0
Section 16 A/D Converter
—
R
4
0
—
R
3
0
REJ09B0275-0500
—
R
2
0
—
R
1
0
—
R
0
0