HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 722

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 20 Clock Pulse Generator
20.4
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of
the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
When setting the multiplication factor, ensure that the clock frequency after multiplication does
not exceed the maximum operating frequency of the chip.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0 (initial value), the setting becomes valid after a transition to software standby
mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0
in SBYCR.
[1] The initial PLL circuit multiplication factor is 1.
[2] A value is set in bits STS2 to STS0 to give the specified transition time.
[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode.
[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
[5] Software standby mode is cleared, and a transition time is secured in accordance with the
[6] After the set transition time has elapsed, the LSI resumes operation using the target
If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in
[3], software standby mode is entered and break exception handling is executed after the
oscillation stabilization time. In this case, the instruction following the SLEEP instruction is
executed after execution of the RTE instruction.
When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits
STC1 and STC0 are rewritten.
20.5
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
Rev. 5.00 Jan 10, 2006 page 696 of 1042
REJ09B0275-0500
setting in STS2 to STS0.
multiplication factor.
PLL Circuit
Medium-Speed Clock Divider