HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 843

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.
A.5
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Instruction
TAS
TRAPA
XOR
XORC
JMP@aa:24
Instruction
2. 5 for concatenated execution, 4 otherwise.
3. An internal operation may require between 0 and 3 additional states, depending on the
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Bus States during Instruction Execution
Mnemonic
TAS
TRAPA #x:2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
preceding instruction.
R:W 2nd
@ERd *
1
4
Internal operation
2 state
2
Instruction
Fetch
I
2
2
1
1
2
1
3
2
1
2
R:W EA
3
Branch
Address Read
J
2
4
Order of execution
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
Rev. 5.00 Jan 10, 2006 page 817 of 1042
Stack
Operation
K
2/3 *
5
1
Byte Data
Access
L
2
Appendix A Instruction Set
6
Word Data
Access
M
REJ09B0275-0500
7
Internal
Operation
N
2
8