HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 499

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Data Transfer Operations
SCI initialization (clocked synchronous mode): Before transmitting and receiving data, you
should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 13.15 shows a sample SCI initialization flowchart.
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
to 0 or set to 1 simultaneously.
1-bit interval elapsed?
Start initialization
Set value in BRR
SMR and SCMR
<Transfer start>
(TE, RE bits 0)
Figure 13.15 Sample SCI Initialization Flowchart
Yes
Wait
No
[4]
[2]
[3]
[1]
Section 13 Serial Communication Interface (SCI)
[1] Set the clock selection in SCR. Be sure
[2] Set the data transfer format in SMR
[3] Write a value corresponding to the bit
[4] Wait at least one bit interval, then set
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
and SCMR.
rate to BRR. Not necessary if an
external clock is used.
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Rev. 5.00 Jan 10, 2006 page 473 of 1042
REJ09B0275-0500