HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 754

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 21B Power-Down Modes [H8S/2626 Group]
21B.4 Sleep Mode
21B.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR
LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other supporting modules do not stop.
21B.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt
exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other
than NMI are masked by the CPU.
Exiting Sleep Mode by RES
stipulated reset input duration, driving the RES pin High starts the CPU performing reset
exception processing.
Exiting Sleep Mode by STBY
to hardware standby mode.
21B.5 Module Stop Mode
21B.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21B.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, A/D converter and HCAN are retained.
After reset clearance, all modules other than DTC are in module stop mode.
Rev. 5.00 Jan 10, 2006 page 728 of 1042
REJ09B0275-0500
RES
RES
RES pin: Setting the RES pin level Low selects the reset state. After the
STBY Pin: When the STBY pin level is driven Low, a transition is made
STBY
STBY