HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 570

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Controller Area Network (HCAN)
Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been
reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after
reset input or recovery from software standby mode, interrupt handling will be performed as soon
as interrupts are enabled by the interrupt controller.
Bit 8
IRR0
0
1
Note:
Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.
Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in HCAN sleep mode.
Bit 4
IRR12
0
1
Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been
overwritten while still unread.
Rev. 5.00 Jan 10, 2006 page 544 of 1042
REJ09B0275-0500
* After reset or hardware standby release, the module stop bit is initialized to 1, and so
the HCAN enters the module stop state.
Description
[Clearing condition]
Writing 1
Hardware reset (HCAN module stop * , software standby)
[Setting condition]
When reset processing is completed after a hardware reset (HCAN module stop * ,
software standby)
Description
CAN bus idle state
[Clearing condition]
Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
(Initial value)
(Initial value)