HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 200

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
7.6
7.6.1
When the H8S/2626 Group or H8S/2623 Group accesses external space , it can insert a 1-state idle
cycle (T
areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By
inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a
long output floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 5.00 Jan 10, 2006 page 174 of 1042
REJ09B0275-0500
CS * (area A)
CS * (area B)
Note: * The CS signals are generated off-chip.
Address bus
Data bus
I
) between bus cycles in the following two cases: (1) when read accesses between different
Idle Cycle
Operation
RD
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
Figure 7.15 Example of Idle Cycle Operation (1)
T
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
CS * (area A)
CS * (area B)
Address bus
Data bus
RD
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
2
T
3
T
Bus cycle B
I
T
1
T
2