HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 51

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
2.1.3
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
2.1.4
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
More general registers and control registers
Expanded address space
Enhanced addressing
Enhanced instructions
Higher speed
Additional control register
Enhanced instructions
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
Normal mode * supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-and-accumulate instruction has been added.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Basic instructions execute twice as fast.
One 8-bit and two 32-bit control registers have been added.
Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-and-accumulate instruction has been added.
Two-bit shift instructions have been added.
Differences from H8/300 CPU
Differences from H8/300H CPU
Rev. 5.00 Jan 10, 2006 page 25 of 1042
REJ09B0275-0500
Section 2 CPU