HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 14

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3
Section 7 Bus Controller
7.1
7.2
7.3
7.4
7.5
Rev. 5.00 Jan 10, 2006 page xii of xxiv
6.2.2
6.2.3
6.2.4
6.2.5
Operation .......................................................................................................................... 133
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Overview........................................................................................................................... 139
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions ........................................................................................................ 143
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Overview of Bus Control .................................................................................................. 154
7.3.1
7.3.2
7.3.3
7.3.4
Basic Bus Interface ........................................................................................................... 158
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Burst ROM Interface......................................................................................................... 171
7.5.1
7.5.2
7.5.3
Break Address Register B (BARB)...................................................................... 130
Break Control Register A (BCRA) ...................................................................... 130
Break Control Register B (BCRB)....................................................................... 132
Module Stop Control Register C (MSTPCRC).................................................... 132
PC Break Interrupt Due to Instruction Fetch ....................................................... 133
PC Break Interrupt Due to Data Access............................................................... 134
Notes on PC Break Interrupt Handling ................................................................ 134
Operation in Transitions to Power-Down Modes ................................................ 135
PC Break Operation in Continuous Data Transfer............................................... 136
When Instruction Execution is Delayed by One State ......................................... 137
Additional Notes .................................................................................................. 138
Features................................................................................................................ 139
Block Diagram ..................................................................................................... 140
Pin Configuration................................................................................................. 141
Register Configuration......................................................................................... 142
Bus Width Control Register (ABWCR)............................................................... 143
Access State Control Register (ASTCR) ............................................................. 144
Wait Control Registers H and L (WCRH, WCRL).............................................. 145
Bus Control Register H (BCRH).......................................................................... 149
Bus Control Register L (BCRL) .......................................................................... 151
Pin Function Control Register (PFCR) ................................................................ 152
Area Partitioning.................................................................................................. 154
Bus Specifications................................................................................................ 155
Memory Interfaces ............................................................................................... 156
Interface Specifications for Each Area ................................................................ 157
Overview.............................................................................................................. 158
Data Size and Data Alignment............................................................................. 158
Valid Strobes........................................................................................................ 160
Basic Timing........................................................................................................ 161
Wait Control ........................................................................................................ 169
Overview.............................................................................................................. 171
Basic Timing........................................................................................................ 171
Wait Control ........................................................................................................ 173
................................................................................................... 139