HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 935

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PMR—PPG Output Mode Register
Bit
Initial value
Read/Write
:
:
:
G3INV
R/W
Group 3 invert
0
1
7
1
Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
G2INV
R/W
Group 2 invert
0
1
6
1
Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
Group 1 invert
0
1
Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)
G1INV
Group 0 invert
R/W
0
1
5
1
Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)
G0INV
R/W
4
1
Group 3 non-overlap
0
1
H'FE27
Normal operation in pulse output group
3 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 3 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
Rev. 5.00 Jan 10, 2006 page 909 of 1042
G3NOV
R/W
3
0
Group 2 non-overlap
0
1
Group 1 non-overlap
Normal operation in pulse output group
2 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 2 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
0
1
Appendix B Internal I/O Register
Group 0 non-overlap
Normal operation in pulse output group
1 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 1 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
G2NOV
0
1
R/W
Normal operation in pulse output group
0 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 0 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
2
0
G1NOV
R/W
REJ09B0275-0500
1
0
G0NOV
R/W
0
0
PPG