upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 23

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

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Single Buffer Transfer Mode (Master, Receive Only) Timing .................................... 492
Single Buffer Transfer Mode (Master, Transmit/Receive) Timing ............................. 493
Single Buffer Transfer Mode (Slave, Transmit Only) Timing ..................................... 494
Single Buffer Transfer Mode (Slave, Receive Only) Timing ...................................... 495
Single Buffer Transfer Mode (Slave, Transmit/Receive) Timing ............................... 496
FIFO Buffer Transfer Mode (Master, Transmit Only) Timing..................................... 497
FIFO Buffer Transfer Mode (Master, Receive Only) Timing...................................... 498
FIFO Buffer Transfer Mode (Master, Transmit/Receive) Timing ............................... 499
FIFO Buffer Transfer Mode (Slave, Transmit Only) Timing....................................... 500
FIFO Buffer Transfer Mode (Slave, Receive Only) Timing........................................ 501
FIFO Buffer Transfer Mode (Slave, Transmit/Receive) Timing ................................. 502
DMA Block Diagram .................................................................................................. 504
DMA Control Register (DMC) Format ....................................................................... 505
IDMEN Bit and NMI Handling .................................................................................... 506
DMA Channel Status Flag Register (DMSF) Format ................................................ 507
DMA Source Address Register (DMSAn) Format (1/2) ............................................ 507
DMA Destination Address Register (DMDAn) Format (1/2) ..................................... 509
DMA Transfer Count Register (DMBCn) Format ...................................................... 510
DMA Addressing Control Register (DMADCn) Format (1/2) .................................... 511
Effect of TDIR Flag on DMA Transfer ....................................................................... 512
DMA Channel Control Register (DMCHCn) Format (1/4) ......................................... 513
DMA Trigger Factor Register (DTFRn) Format ........................................................ 517
TCS Bit and INTDMAn Generation ........................................................................... 521
Single Transfer Mode Example (1 Channel) ............................................................. 522
Single Transfer Mode Example (3 Channels)............................................................ 522
Fixed Channel Transfer Example (2 Channels) ........................................................ 523
Fixed Channel Transfer Mode Example (3 Channels) .............................................. 523
Block Transfer Example (2 Channels)....................................................................... 524
Block Diagram of CAN Module.................................................................................. 527
Composition of Layers............................................................................................... 528
Data Frame ............................................................................................................... 529
Remote Frame .......................................................................................................... 530
Start of Frame (SOF)................................................................................................. 530
Arbitration Field (in Standard Format Mode) ............................................................. 531
Arbitration Field (in Extended Format Mode)............................................................. 531
Control Field .............................................................................................................. 532
Data Field .................................................................................................................. 533
CRC Field .................................................................................................................. 533
ACK Field .................................................................................................................. 534
End of Frame (EOF) .................................................................................................. 534
Interframe Space (Error Active Node) ....................................................................... 535
Interframe Space (Error Passive Node) .................................................................... 536
Error Frame ............................................................................................................... 537
Overload Frame ........................................................................................................ 538
Recovery from Bus-off State Through Normal Recovery Sequence ......................... 545
Segment Setting ........................................................................................................ 547
Reference: Configuration of Data Bit Time Defined by CAN Specification................ 548
Adjusting Synchronization of Data Bit ....................................................................... 549
Resynchronization ..................................................................................................... 550
Connection to CAN Bus ............................................................................................ 551
CAN Global Control Register (CnGMCTRL) Format (1/2)......................................... 588
CAN Global Clock Selection Register (CnGMCS) Format ....................................... 590
CAN Global Automatic Block Transmission Control Register (CnGMABT)
Format (1/2)............................................................................................................... 591
CAN Global Automatic Block Transmission Delay Register (CnGMABTD) Format . 593
CAN Module Mask Control Register (CnMASKaL, CnMASKaH)
(a = 1, 2, 3, or 4) Format (1/2) ................................................................................... 594
CAN Module Control Register (CnCTRL) Format (1/4) ............................................. 596
User’s Manual U16702EE3V2UD00
23