upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 840

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

RETI
SAR
SASF
SATADD
SATSUB
SATSUBI imm16,reg1,reg2
SATSUBR reg1,reg2
SETF
SET1
SHL
SHR
SLD.B
SLD.BU
SLD.H
SLD.HU
SLD.W
SST.B
SST.H
SST.W
ST.B
ST.H
ST.W
STSR
SUB
SUBR
840
Mnemonic
(3/4)
reg1,reg2
imm5,reg2
cccc,reg2
reg1,reg2
imm5,reg2
reg1,reg2
cccc,reg2
bit#3,disp16[reg1]
reg2,[reg1]
reg1,reg2
imm5,reg2
reg1,reg2
imm5,reg2
disp7[ep],reg2
disp4[ep],reg2
disp8[ep],reg2
disp5[ep],reg2
disp8[ep],reg2
reg2,disp7[ep]
reg2,disp8[ep]
reg2,disp8[ep]
reg2,disp16[reg1]
reg2,disp16[reg1]
reg2,disp16[reg1]
regID,reg2
reg1,reg2
reg1,reg2
Operand
Note 18
Note 19
rrrrr0000111dddd
Notes 18, 20
Note 21
Note 19
Note 21
Note 8
Note 8
0000011111100000
0000000101000000
rrrrr111111RRRRR
0000000010100000
rrrrr010101iiiii
rrrrr1111110cccc
0000001000000000
rrrrr000110RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1])
rrrrr010001iiiii GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
rrrrr000101RRRRR GR[reg2]←saturated(GR[reg2]–GR[reg1])
rrrrr110011RRRRR
iiiiiiiiiiiiiiii
rrrrr000100RRRRR GR[reg2]←saturated(GR[reg1]–GR[reg2])
rrrrr1111110cccc
0000000000000000
00bbb111110RRRRR
dddddddddddddddd
rrrrr111111RRRRR
0000000011100000
rrrrr111111RRRRR
0000000011000000
rrrrr010110iiiii
rrrrr111111RRRRR
0000000010000000
rrrrr010100iiiii
rrrrr0110ddddddd
rrrrr0000110dddd
rrrrr1000ddddddd
rrrrr1010dddddd0
rrrrr0111ddddddd
rrrrr1001ddddddd
rrrrr1010dddddd1
rrrrr111010RRRRR
dddddddddddddddd
rrrrr111011RRRRR
ddddddddddddddd0
rrrrr111011RRRRR
ddddddddddddddd1
rrrrr111111RRRRR
0000000001000000
rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1]
rrrrr001100RRRRR GR[reg2]←GR[reg1]–GR[reg2]
Opcode
Appendix A
User’s Manual U16702EE3V2UD00
if PSW.EP=1
GR[reg2]←GR[reg2] arithmetically shift right
GR[reg2]←GR[reg2] arithmetically shift right
if conditions are satisfied
GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
If conditions are satisfied
adr←GR[reg1] + sign-extend(disp16)
Z flag←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
GR[reg2]←GR[reg2] logically shift left by
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
GR[reg2]←GR[reg2] logically shift right by
adr←ep + zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
adr←ep + zero-extend(disp4)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
adr←ep + zero-extend(disp8)
GR[reg2]←sign-extend(Load-memory(adr,Half-word))
adr←ep+zero-extend(disp5)
GR[reg2]←zero-extend(Load-memory(adr,Half-word))
adr←ep + zero-extend(disp8)
GR[reg2]←Load-memory(adr,Word)
adr←ep + zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
adr←ep + zero-extend(disp8)
Store-memory(adr,GR[reg2],Half-word)
adr←ep + zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
adr←GR[reg1] + sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
adr←GR[reg1] + sign-extend(disp16)
Store-memory (adr,GR[reg2], Half-word)
adr←GR[reg1] + sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
GR[reg2]←SR[regID]
then PC ←EIPC
else if PSW.NP=1
then GR[reg2]←(GR[reg2]Logically shift left by 1)
else GR[reg2]←(GR[reg2]Logically shift left by 1)
then GR[reg2]←00000001H
else GR[reg2]←00000000H
PSW ←EIPSW
then PC ←FEPC
else PC←EIPC
PSW ←FEPSW
PSW ←EIPSW
Instruction Set List
OR 00000001H
OR 00000000H
by GR[reg1]
by zero-extend (imm5)
zero-extend(imm5)
zero-extend(imm5)
Operation
Note
Note
3
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
Execution
i
Clock
Note
Note
3
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
r
Note
Note
Note
Note
Note
Note
Note
3
1
1
1
1
1
1
1
1
1
3
3
3
3
1
1
1
1
9
9
9
9
9
1
1
1
1
1
1
1
1
1
l
CY OV S
R
×
×
×
×
×
×
×
×
×
×
×
×
×
R
0
0
×
×
×
×
×
0
0
0
0
×
×
Flags
R
×
×
×
×
×
×
×
×
×
×
×
×
×
R
Z SAT
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
R
×
×
×
×
×