upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 506

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
Cautions: 1. Do not set the STPSET and STPCLR bits at the same time. If both bits are set at
Remark:
Cautions: 1. Do not set the IDMEN bit while POWER = 1.
506
processing
processing
STPCLR
POWER
DMMRQ
DMMRQ
STPDIS
IDMEN=0:
IDMEN=1:
0
1
0
1
NMI
NMI
NMI
NMI
2. If STPCLR is set at the same time as the occurrence of a NMI that would set the
This bit is a trigger bit only. When reading the bit, the read value is always 0.
2. Disable all DMA transfers (clear EN bit of DMCHCn registers) before stopping the
the same time, STPCLR has priority over STPSET.
STPDIS bit, the STPDIS bit will not be set.
DMA (POWER cleared to 0)
CPU
CPU
No change
Release all interrupted and stopped DMA transfers and resume operation.
When this bit set to 1, SPTDIS bit is cleared to 0 and pending DMA transfers are resumed.
The clock supply to the DMA controller is stopped and all operation disabled. The DMA
channel control registers (DMCHCn) and the internal circuits are reset.
The clock supply to the DMA controller is started and the DMA operation enabled.
Set the POWER bit to 1 before initializing and using the DMA controller.
NMI detected, but processing delayed until DMA is finished
CPU
CPU
CPU
CPU
NMI interrupts DMA cycle immediately
Chapter 15 DMA Functions (DMA Controller)
Figure 15-3: IDMEN Bit and NMI Handling
DMA
DMA
User’s Manual U16702EE3V2UD00
DMA
DMA
Transfer Interruption Clear Trigger Bit
DMA
CPU
DMA Controller Operation Enable
DMA
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMA
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU

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