upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 67

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(4)
Note: During saturated operation, the saturated operation results are determined by the contents of the OV
Bit position
31 to 8
PSW
Program status word (PSW)
A program status word (PSW) is a collection of flags that indicate the program status (instruction
execution result) and the CPU status.
When the contents of this register are changed using the LDSR instruction, the new contents
become valid immediately following completion of the LDSR instruction execution. However, if the
ID flag is set to 1, interrupt request acknowledgement during LDSR instruction execution is prohib-
ited.
Bits 31 to 8 are reserved (fixed to 0) for future function expansion.
7
6
5
4
3
2
1
0
flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. This
is explained on the following table.
31
Flag name
SAT
OV
S
RFU
NP
CY
EP
Note
ID
Z
Note
Note
Figure 3-6: Program Status Word (PSW) Format (1/2)
Reserved field. Fixed to 0.
Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1
when an NMI request is acknowledged, disabling multiple interrupts.
Indicates that an exception is being processed. This bit is set to 1 when an excep-
tion occurs. Even if this bit is set, interrupt requests are acknowledged.
Indicates whether a maskable interrupt can be acknowledged.
Indicates that the result of a saturation operation has overflowed and is saturated.
Because this is a cumulative flag, it is set to 1 when the result of a saturation opera-
tion instruction is saturated, and is not cleared to 0 even if the subsequent operation
result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither
set to 1 nor cleared to 0 by execution of an arithmetic operation instruction.
Indicates whether a carry or a borrow occurs as a result of an operation.
Indicates whether an overflow occurs during operation.
Indicates whether the result of an operation is negative.
Indicates whether the result of an operation is 0.
0: NMI is not being serviced.
1: NMI is being serviced.
0: Exception is not being processed.
1: Exception is being processed.
0: Interrupt enabled
1: Interrupt disabled
0: Not saturated
1: Saturated
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
0: Overflow does not occur.
1: Overflow occurs.
0: The result is positive or 0.
1: The result is negative.
0: The result is not 0.
1: The result is 0.
User’s Manual U16702EE3V2UD00
Chapter 3 CPU Function
RFU
Meaning
8 7
NP
EP
6
ID
5
SAT
4
CY
3
OV
2
S Z
1
0
00000021H
After reset
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