upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 743

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
19.3.2 Reset operation by WDT2RES signal
When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 over-
flow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the ini-
tial status.
Following watchdog timer 2 overflow, the reset status is entered and lasts the period of time predeter-
mined by the analog delay, then the reset status is automatically released. Following reset release, the
CPU starts program execution after securing the oscillation stabilization time (initial value of OSTS reg-
ister: 2
The main clock oscillator is not stopped during the reset period.
Note: Because the V850E/RS1 supports a boot swap function, the firmware uses part of the internal
Main clock oscillator (f
Ring-OSC generator
Peripheral clock (f
Internal system clock (f
CPU clock (f
CPU
Watchdog timer 2
Internal RAM
I/O lines (ports/alternate-function
pins)
On-chip peripheral I/O registers
Other on-chip peripheral functions Operation stops
13
RAM after the internal system reset is released. Therefore, the contents of some areas (RAM
size is 3FC800H-3FC895H into 10K byte and 3FB000H-3FB095H into 16K byte and 2K byte
down from the uppermost address 3FEFFFH- 3FE7FFH) of the RAM are not retained even
when power-on reset is executed.
/f
X
) of the main clock oscillator.
CPU
Item
)
Table 19-2: Hardware Status During WDT2RES Signal Generation
XX
to f
X
CLK
)
XX
/1,024)
),
User’s Manual U16702EE3V2UD00
Continues oscillation
Continues oscillation
Operation stops
Operation stops
Initialized
Operation stops
undefined if power-on reset or writing data to RAM (by CPU) and reset input
conflict (data is damaged).
Otherwise value immediately after reset input is retained
High impedance
Initialized to specified status, OCDM register is set (01H).
Chapter 19 RESET Function
During Reset
Operation starts after securing of oscilla-
tion stabilization time (initialized to f
Operation starts after securing of oscilla-
tion stabilization time (initialized to f
Program execution starts after securing of
oscillation stabilization time
Operation starts
Operation can be started after securing
oscillation stabilization time
After Reset
Note
.
XX
XX
x 4)
x 4)
743

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