upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 317

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

TQ0OPT0 TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0
TQ1OPT0 TQ1CCS3 TQ1CCS2 TQ1CCS1 TQ1CCS0
(6)
Cautions: 1. Rewrite bits TQnCCS3 to TQnCCS0 when TQnCE = 0. (The same value can be
Remark:
Symbol
Symbol
The TQnCCSm bit setting is valid only in the free-running mode.
Set (1)
Reset (0)
• The TQnOVF bit is reset when the 16-bit counter value overflows from FFFFH to 0000H in the free-
• As soon as the TQnOVF bit has been set to 1, an interrupt request signal (INTTQnOV) is generated.
• The TQnOVF bit is not cleared even when the TQnOVF bit and the TQnOPT0 register are read when
• The TQnOVF bit can be both read and written, but 1 cannot be written to the TQnOVF bit from the
TQnCCSm
Timer Q option register 0 (TQnOPT0)
The TQnOPT0 register is an 8-bit register that selects a capture or compare operation, and
detects an overflow.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
TQnOVF
running mode or the pulse width measurement mode.
The INTTQnOV signal is not generated in any mode other than the free-running mode and pulse width
measurement mode.
TQnOVF = 1.
CPU. Writing 1 has no influence on the operation of timer Q.
0
1
2. Be sure to clear bits 1, 2 and 3 to 0.
n = 0, 1
m = 0 to 3
7
7
written when TQnCE = 1.) If rewriting was mistakenly performed, set TQnCE = 0
and then set the bits again.
Compare register
Capture register
Overflow occurrence
0 written to TQnOVF bit or TQnCE = 0
Figure 8-12: Timer Q Option Register 0 (TQnOPT0) Format
6
6
Selection of capture or compare operation of TQnCCRm register
Chapter 8 16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
5
5
4
4
Detection of Timer Q overflow
3
0
3
0
2
0
2
0
1
0
1
0
TQ0OVF FFFFF545H R/W 00H
TQ1OVF FFFFF615H R/W 00H
<0>
<0>
Address
Address
R/W
R/W
reset
reset
After
After
317