upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 27

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Table 1-1:
Table 1-2:
Table 2-1:
Table 2-2:
Table 2-3:
Table 2-4:
Table 2-5:
Table 3-1:
Table 3-2:
Table 3-3:
Table 3-4:
Table 4-1:
Table 4-2:
Table 4-3:
Table 4-4:
Table 4-5:
Table 4-6:
Table 4-7:
Table 4-8:
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 6-1:
Table 6-2:
Table 6-3:
Table 7-1:
Table 7-2:
Table 7-3:
Table 7-4:
Table 7-5:
Table 8-1:
Table 8-2:
Table 8-3:
Table 8-4:
Table 8-5:
Table 9-1:
Table 10-1:
Table 10-2:
Table 11-1:
Table 11-2:
Table 11-3:
Table 12-1:
Table 12-2:
Table 12-3:
Table 12-4:
Table 12-5:
Table 12-6:
Table 13-1:
Table 13-2:
Table 13-3:
Table 14-1:
Table 14-2:
Table 14-3:
Table 15-1:
Product Versions ............................................................................................................ 30
Port Functions and Control Function .............................................................................. 38
Pin of Power Supplies .................................................................................................... 39
Port Pins ......................................................................................................................... 39
Non-port pins .................................................................................................................. 41
Pin Operation States in Various Modes.......................................................................... 44
Pin I/O Circuit Types....................................................................................................... 57
Program Registers.......................................................................................................... 63
System Register Numbers.............................................................................................. 64
Access Conditions .......................................................................................................... 90
Peripheral I/O Registers ................................................................................................. 93
I/O Buffer Power Supplies for Pins ............................................................................... 106
Control Register Setting ............................................................................................... 107
Port Configuration......................................................................................................... 110
Valid Edge Specification............................................................................................... 117
Valid Edge Specification............................................................................................... 123
Valid Edge Specification............................................................................................... 132
Valid Edge Specification............................................................................................... 154
Port Type ...................................................................................................................... 170
Bus Control Pins (Multiplexed Bus) .............................................................................. 208
Pin Status When Internal ROM, Internal RAM, or Peripheral I/O Is Accessed............. 208
Allocation of the Memory Blocks .................................................................................. 210
Bus Priority ................................................................................................................... 225
Divide and PLL0 Time Value ........................................................................................ 252
Divide and PLL1 Time Value ........................................................................................ 252
Divide Value of f
Configuration of TMP0 to TMP3 ................................................................................... 256
TMP Pin List ................................................................................................................. 256
Tuned Operation Mode of Timer .................................................................................. 299
Timer Modes Usable in Tuned Operation Mode........................................................... 299
Timer Output Functions ................................................................................................ 300
TMQ Configuration ....................................................................................................... 304
TMQ Pin List................................................................................................................. 304
Tuned Operation Mode of Timer .................................................................................. 351
Timer Modes Usable in Tuned Operation Mode........................................................... 351
Timer Output Functions ................................................................................................ 352
Configuration of TMM ................................................................................................... 356
Configuration of Watchdog Timer 2.............................................................................. 360
Watchdog Timer 2 Clock Selection .............................................................................. 362
Configuration of A/D Converter .................................................................................... 369
Software Trigger Mode (ADSCM0H Register Configuration) ....................................... 381
External Trigger Mode (ADSCM0H and SELCNT1 Registers Configuration) .............. 381
Configuration of UARTA0 and UARTA1....................................................................... 404
List of Pins of Asynchronous Serial Interface A............................................................ 404
Interrupts and Their Default Priority.............................................................................. 415
Reception Error Causes ............................................................................................... 421
Baud Rate Generator Set Data .................................................................................... 427
Permissible Maximum/Minimum Baud Rate Error........................................................ 429
Configuration of CSIB0, CSIB1 .................................................................................... 431
List of 3-Wire Serial Interface Pins ............................................................................... 432
Interrupts and their Default Priority............................................................................... 442
Input/Output Pins of the CSI3....................................................................................... 464
CSI30............................................................................................................................ 465
CSI31............................................................................................................................ 465
Interrupt Source for DMA Trigger Factor Register (DTFRn)......................................... 518
PLL
User’s Manual U16702EE3V2UD00
Frequency and f
List of Tables
PCL
Frequency.................................................... 254
27