upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 92

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

3.5 Programmable I/O Area
The V850E/RS1 includes an additional memory area for the control of on-chip peripherals. The base
address of this area is located in the external memory space.
A control register setting is required to enable this additional memory.
Control registers for the following on-chip peripherals are implemented in the Programmable I/O area.
3.5.1 Programmable peripheral I/O control register (BPC)
This 16-bit register specifies selection of the Programmable I/O area.
The BPC register can be read or written only in 16-bit units.
RESET input clears BPC to 0000H.
To use the CAN built-in interfaces, set PA15 to 1 by writing the BPC register with a 16-bit memory
manipulation instruction.
To disable access to the CAN RAM and CAN registers, clear PA15 to 0 by writing 0000H to the
BPC register with a 16-bit memory manipulation instruction.
The mapping of the CAN RAM and registers can be shown in section 3.4.4 ”Memory map” on
page 78.
For example, if BPC = 0x8FFB, the programmable area is set to 3FEC000H.
Caution:
Remark:
92
Symbol
BPC
R/W
Bit position
• CAN
15
0
PA15
PA07
R/W
R/W
15
Figure 3-30: Programmable Peripheral I/O Control Register (BPC) Format
When using the CAN controller (PA15 = 1), be sure to set 8FFBH to this register.
When not using the CAN controller (PA15 = 0), be sure to set 0000H to this register.
The programmable peripheral I/O area is fixed by hardware in the V850E core
in 3FEC000H to 3FEEFFFH. However, be sure to set 8FFBH to this register when
using the CAN controller because it is possible to write it in bit 13 to bit 0 of this register in
tool (ICE).
7
Bit name
PA13 to
PA15
PA00
PA06
R/W
R/W
14
0
6
PA13
PA05
R/W
R/W
Enables/disables usage of programmable peripheral I/O area
Specify an address in programmable peripheral I/O area
(correspond to A27 to A14 respectively)
13
5
PA15
0
1
User’s Manual U16702EE3V2UD00
PA12
PA04
R/W
R/W
Chapter 3 CPU Function
12
4
Usage of programmable peripheral I/O area is disabled
Usage of programmable peripheral I/O area is enabled
PA11
PA03
R/W
R/W
11
3
Usage of programmable peripheral I/O area
PA10
PA02
R/W
R/W
10
2
Function
PA09
PA01
R/W
R/W
9
1
PA08
PA00
R/W
R/W
8
0
FFFFF064H
Address
After reset
0000H