upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 248

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(5)
Caution:
248
Symbol
OCKS0
R/W
OCKSEN0
OCKSTH0
Clock selection register 0 (OCKS0)
This is an 8-bit register that controls the operation enable and clock input selection for PLL0.
OCKS01
0
1
0
1
0
0
1
1
R
7
0
When PLL mode operation is enabled, OCKS0 register value must not be changed.
PLL0 operation Disable
PLL0 operation Enable
Output clock is divided clock by setting OCKS01 & OCKS00
Output clock is through
OCKS00
R
6
0
Figure 6-14: Clock Selection Register 0 (OCKS0) Format
0
1
0
1
R
5
0
OCKSEN0 OCKSTH0
User’s Manual U16702EE3V2UD00
Chapter 6 Clock Generator
R/W
4
Specified for output clock through or divide
Specified for execution enable
R/W
3
Specified for divider factor
R
2
0
OCKS01 OCKS00 FFFFF860H
f
f
f
f
X
X
X
X
/2
/3
/4
/5
R/W
1
R/W
0
Address
After reset
11H