upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 705

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

17.3.6 In-service priority register (ISPR)
This register holds the priority level of the maskable interrupt currently acknowledged. When an inter-
rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt
request is set to 1 and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest
priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned
from non-maskable interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
Remark:
Caution:
ISPR
After reset: 00H
n = 0 to 7 (priority level)
If an interrupt is acknowledged while the ISPR register is being read in the interrupt
enabled (EI) status, the value of the ISPR register after the bits of the register have
been set by acknowledging the interrupt may be read. To accurately read the value of
the ISPR register before an interrupt is acknowledged, read the register while inter-
rupts are disable (DI).
ISPR7
ISPRn
<7>
Figure 17-12: In-Service Priority Register (ISPR) Format
0
1
Chapter 17 Interrupt/Exception Processing Function
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
ISPR6
<6>
User’s Manual U16702EE3V2UD00
ISPR5
<5>
R
Priority of interrupt currently acknowledged
Address:
ISPR4
<4>
ISPR3
<3>
ISPR2
<2>
FFFFF1FAH
ISPR1
<1>
ISPR0
<0>
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