upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 26

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

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Communication Command ........................................................................................ 764
Block Diagram of On-chip Debug Function ............................................................... 769
On-Chip Debug Mode Register (OCDM) Format ..................................................... 771
P911/ DRST Built-in Pull Down Resistor ................................................................... 772
Timing Chart of Selecting Normal Operation Mode................................................... 773
Timing Chart of Selecting On-Chip Debug Mode ...................................................... 773
Connection to N-Wire Emulator (NEC Electronics IE-V850E1-CD-NW:
N-Wire Card) ............................................................................................................. 774
Pin Configuration of Connector for Emulator Connection (Target System Side)....... 775
Example of Recommended Emulator Connection Circuit ......................................... 777
Block Diagram of Power-on-Clear Circuit.................................................................. 780
Block Diagram of Low-Voltage Detector.................................................................... 781
Low-Voltage Detection Register (LVIM) Format ....................................................... 782
Low-Voltage Detection Level Selection Register (LVIS) Format .............................. 783
Internal RAM Data Status Register (RAMS) Format ................................................ 783
Peripheral Emulation Register 1 (PEMU1) ............................................................... 784
Operation Timing of Low-Voltage Detector (LVIMD = 1) ........................................... 786
Operation Timing of Low-Voltage Detector (LVIMD = 0) ........................................... 787
Operation Timing of RAM Retention Voltage Detection Function ............................. 788
Block Diagram of Clock Monitor ................................................................................ 789
Clock Monitor Mode Register (CLM) Format ............................................................ 790
When Oscillation of Main Clock Is Stopped............................................................... 791
Operation in Software STOP Mode or After Software STOP Mode Is Released ...... 792
Block Diagram of CRC Register ................................................................................ 793
CRC Input Register (CRCIN) Format ....................................................................... 794
CRC Data Register (CRCD) Format ......................................................................... 794
CRC Operation Circuit Operation Example (LSB First)............................................. 795
CRC Operation Flow ................................................................................................. 796
CRC Transmission Example ..................................................................................... 797
Recommended Oscillator Connection (Ceramic or Crystal Resonator) .................... 802
Voltage Regulator Startup Timing ............................................................................. 803
AC Test Conditions.................................................................................................... 807
Input Rise and Fall Time............................................................................................ 808
Output Rise and Fall Time......................................................................................... 808
RESET, Interrupt, NMI and FLMD0 Timing ............................................................... 809
Read Cycle (CLKOUT Asynchronous, 1 Wait) .......................................................... 812
Write Cycle (CLKOUT Asynchronous, 1 WAIT) ........................................................ 813
Bus Hold .................................................................................................................... 814
CSIBn Timing (CBnCKP=0, CBnDAP=0) .................................................................. 816
CAN Internal Timing .................................................................................................. 817
CSI3n Timings (1/2)................................................................................................... 819
CS3n3 - CS3n0 Pins Timings (1/3) ........................................................................... 821
Power-on-clear (POC) Waveform.............................................................................. 825
Low-Voltage Indicator (LVI) Waveform...................................................................... 826
Power on Sequence .................................................................................................. 827
Flash EPROM Serial Programming Operation Characteristics ................................. 829
Package Drawing ...................................................................................................... 831
Timing of Internal Reset Signal Generation by Power-on-Clear Circuit ................... 780
User’s Manual U16702EE3V2UD00