upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 597

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Remarks: 1. The TSTAT bit is set to 1 under the following conditions (timing):
Remarks: 1. The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or
Remark:
CCERC
TSTAT
0
1
0
1
AL
0
1
2. The TSTAT bit is cleared to 0 under the following conditions (timing):
2. When the CnERC and CnINFO registers have been cleared, the CCERC bit is also
3. The CCERC bit can be set to 1 at the same time as a request to change the initialization
4. If the CCERC bit is set to 1 immediately after the INIT mode is entered in the self test
The AL bit is valid only in the single-shot mode.
The CnERC and CnINFO registers are not cleared in the initialization mode.
The CnERC and CnINFO registers are cleared in the initialization mode.
Transmission is stopped.
Transmission is in progress.
Figure 16-28: CAN Module Control Register (CnCTRL) Format (2/4)
- The SOF bit of a transmit frame is detected
- The first bit of an error flag is detected during a transmit frame
- During transition to bus-off state
- On occurrence of arbitration loss in transmit frame
- On detection of recessive level at the second bit of the interframe space
- On transition to the initialization mode at the first bit of the interframe space
forced recovery from the bus-off state. This bit can be set to 1 only in the initialization
mode.
cleared to 0 automatically.
mode to an operation mode is made.
mode, the receive data may be corrupted.
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
User’s Manual U16702EE3V2UD00
Chapter 16 FCAN Controller
Bit to set operation in case of arbitration loss
Transmission status bit
Error counter clear bit
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