upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 688

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

17.2 Non-Maskable Interrupts
A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the
interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the
other interrupts.
This product has the following two non-maskable interrupts.
The valid edge of the NMI pin can be selected from three types: “rising edge”, “falling edge”, and “both
edges”.
The non-maskable interrupt generated by overflow of the watchdog timer (INTWDT2) functions when
the WDM21 and WDM20 bits of the watchdog timer mode register 2 (WDTM2) are set to “01”.
If two or more non-maskable interrupts occur at the same time, the interrupt with the higher priority is
serviced, as follows (the interrupt with the lower priority is ignored).
If a new NMI or INTWDT2 request is issued while a NMI is being serviced, it is serviced as follows.
(1)
(2)
Caution:
688
• NMI pin input (NMI)
• Non-maskable interrupt request generated by overflow of watchdog timer (INTWDT2)
NMI > INTWDT2
If new NMI request is issued while NMI is being serviced
The new NMI request is (strike through: held pending) serviced, regardless of the value of the NP
bit of the program status word (PSW) in the CPU. The pending NMI interrupt is acknowledged
after the NMI currently under execution has been serviced. The new NMI interrupts the current
NMI routine.
A system reset has to be executed in this typical case of nested NMI interrupt.
If INTWDT2 request is issued while NMI is being serviced
The INTWDT2 request is held pending. if the NP bit of the PSW remains set (1) while the NMI
whatever the NP bit is while the NMI, which has an higher priority, is being serviced. The pending
INTWDT2 request is acknowledged after the NMI currently under execution has been serviced.
Figure 17-1: Non-Maskable Interrupt Request Acknowledgement Operation (1/2)
If a non-maskable interrupt request is generated, the values of the PC and PSW are
saved to the NMI status save registers (FEPC and FEPSW). Therefore, reset the sys-
tem after the interrupt has been serviced.
(a) NMI and INTWDT2 requests generated at the same time
Chapter 17 Interrupt/Exception Processing Function
NMI and INTWDT2 requests
(generated simultaneously)
User’s Manual U16702EE3V2UD00
Main routine
System reset
NMI servicing