upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 231

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(3)
Notes: 1. Upon detection of a low level in the T2 and T3 states of HLDRQ (sampling timing), the
Remarks: 1. The circles indicate the sampling timing when 0 is set for the programmable wait.
AD15-AD0
CLKOUT
HLDRG
HLDAK
Bus hold cycle
ASTB
CSn
RD
2. WR0 and WR1 output a low level as shown in the above timing chart when target data
3. This idle state (TI) does not depend on the BCC register settings.
operation moves on to the bus hold cycle after the T3 state ends. Thereafter, upon detection
of a low level or high level in the TH state (sampling timing), the bus hold status is
maintained after the TH state ends, or the bus cycle is restarted.
access is performed. At all other times, these pins output a high level.
2. The broken line indicates high impedance.
A1
T1
Figure 5-14: Bus Hold Timing (Bus Size: 16 bit)
T2
D1
User’s Manual U16702EE3V2UD00
Chapter 5 Bus Control Function
T3
TI
Unde-
fined
Note 1
all1
TH
TH
Bus hold
TH
TH
TI
Unde-
fined
all1
Note 1
A2
T1
T2
D2
T3
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