upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 287

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

7.5.6 PWM mode (TPnMD2 to TPnMD0 = 110)
In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used to set the duty factor and
TMPn capture/compare register 0 (TPnCCR0) is used to set the cycle.
By using these two registers and operating the timer, variable-duty PWM is output.
Rewriting the TPnCCR0 and TPnCCR1 registers is enabled when TPnCE = 1.
So that the set values of the TPnCCR0 and TPnCCR1 registers are compared with the value of the
16-bit counter (reloaded to the CCR0 and CCR1 buffer registers), the TPnCCR0 register must be
rewritten and then a value must be written to the TPnCCR1 register before the value of the 16-bit
counter matches the value of the TPnCCR0 register.
The values of the TPnCCR0 and TPnCCR1 registers are reloaded when the value of the TPnCCR0
register later matches the value of the 16-bit counter. Whether the next reload timing is made valid or
not is controlled by writing to the TPnCCR1 register. Therefore, write the same value to the TPnCCR1
register even when only the value of the TPnCCR0 register needs to be rewritten. Reload is invalid
when only the value of the TPnCCR0 register is rewritten. To stop timer P, clear TPnCE to 0. The
waveform of PWM is output from the TOPn1 pin. The TOPn0 pin produces a toggle output when the
16-bit counter matches the TPnCCR0 register.
In the PWM mode, the TPnCCR0 and TPnCCR1 registers are used only as compare registers. They
cannot be used as capture registers.
(a) When values of TPnCCR0, TPnCCR1 registers are not rewritten during timer operation
Figure 7-25: Flowchart of Basic Operation in PWM Mode (1/2)
Match between 16-bit counter and CCR0
buffer register,16-bit counter clear & start
• Clock selection
• PWM mode settings
• Compare register setting
Match between 16-bit counter and CCR1
buffer register, TOPn1 low-level output
(TPnCTL0: TPnCKS2 to TPnCKS0)
(TPnCTL1: TPnMD2 to TPnMD0 = 100)
(TPnCCR0, TPnCCR1)
Timer operation enable (TPnCE = 1)
→ Transfer of TPnCCR0, TPnCCR1
Chapter 7 16-Bit Timer/Event Counter P
values to CCR0 buffer register
and CCR1 buffer register
User’s Manual U16702EE3V2UD00
TOPn1 high-level output
Initial settings
START
INTTPnCC0 output
INTTPnCC1 output
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