upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 428

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(7)
Caution:
428
Permissible baud rate range for reception
The permissible baud rate error during reception is shown below.
After the start bit is detected, the counter set by the UAnCTL2 register determines the latch timing
of the receive data, as shown in Figure 12-17. If the last data (stop bit) is received at this latch tim-
ing, the data can be correctly received.
Assuming 11 bits of data are to be received, the theoretical baud rate is as follows.
FL = (Brate) – 1
Brate: Baud rate of UARTAn (n = 0 to 1)
k:
FL:
Margin of latch timing: 2 clocks
Permissible minimum transfer rate:
Transfer rate
transfer rate
transfer rate
Permissible
Permissible
of UARTAn
maximum
minimum
Be sure to set the baud rate error for reception to within the permissible error range,
by using the expressions shown below.
Set value of UAnCTL2 (n = 0 to 1)
1-bit data length
Figure 12-17: Permissible Baud Rate Range for Reception
Chapter 12 Asynchronous Serial Interface A (UARTA)
Start bit
Start bit
Start bit
timing
Latch
Flmin = 11 × FL –
User’s Manual U16702EE3V2UD00
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
k - 2
2k
1 data frame (11 × FL)
FLmin
× FL =
FLmax
21k + 2
Bit 7
2k
Bit 7
Bit 7
Parity bit
FL
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit