upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 731

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

18.5 IDLE2 Mode
18.5.1 Setting and operation status
The IDLE2 mode is set by clearing the PSM1, 0 bit of the power save mode register (PSMR) to 10 and
setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode.
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL and other
on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was
set are retained. Because the IDLE2 stops operation of the on-chip peripheral functions, it reduces the
current consumption to a level lower than the IDLE1 mode.
Table 18-6 shows the operation status in the IDLE2 mode.
The IDLE2 mode can reduce the current consumption more than the HALT mode because it stops the
operation of the on-chip peripheral functions. PLL stop, so the normal operation mode needs PLL setup
time when the HALT mode is released.
Caution:
18.5.2 Releasing IDLE2 mode
The IDLE2 mode is released by a non-maskable interrupt request (NMI pin input, INTWDT2
occurrence), unmasked external interrupt request (INTP0 to INTP7 pin input), unmasked internal
interrupt request from the peripheral functions operable in the software IDLE2 mode, or reset signals.
After the IDLE2 mode has been released, the normal operation mode is restored after the oscillation
stabilization time has been secured.
(1)
Caution:
Releasing IDLE2 mode by non-maskable interrupt request or unmasked maskable interrupt
request
The IDLE2 mode is released by a non-maskable interrupt request or an unmasked maskable
interrupt request, regardless of the priority of the interrupt request. If the IDLE2 mode is set in an
interrupt servicing routine, however, an interrupt request that is issued later is processed as
follows.
(a) If an interrupt request with a priority lower than that of the interrupt request currently being
(b) If an interrupt request with a priority higher than that of the interrupt request currently being
serviced is issued, only the IDLE2 mode is released, and that interrupt request is not
acknowledged. The interrupt request itself is retained.
serviced is issued (including a non-maskable interrupt request), the IDLE2 mode is released
and that interrupt request is acknowledged.
Insert five or more NOP instructions after the instruction that stores data in the PSC
register to set the IDLE2 mode.
An interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI1M,
and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released.
User’s Manual U16702EE3V2UD00
Chapter 18 Standby Function
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