upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 513

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(7)
Cautions: 1. Write to TCS bit is permitted only when POWER bit = 0.
DMCHCn
Symbol
R/W
RQST
DMA channel control register (DMCHCn)
The DMCHCn register controls the DMA transfer operation mode. It can be read or written in 8-bit
or 1-bit units.
The RQST, ACF, FCLR, STG and EN bits are initialized by POWER=0. Initial value is 00H by reset.
The DMA controller has the option to mirror the selected input trigger (IFCn[5:0] bits of the DTFRn
register) to the INTDMA signal. This mirroring is independent from the status of the DMA channel
(disabled, enabled, DMA in progress or ended). The mirror function is used in devices where DMA
interrupts are to be shared with interrupts also serving as interrupt request signals to the DMA
controller.
For V850E/RS1, there is no sharing of interrupts needed, as each of the DMA channels has its
own interrupt assigned on interrupt controller side. Therefore it is highly recommended NOT to use
the TCS=0 setting.
Please refer to section 15.4.4
ing timing of the DMA interrupt.
TCS
0
1
0
1
2. Before changing the TCS bit, mask the corresponding INTDMAn interrupt. After
INTDMAn is a direct mirror of the selected DMA request input signal of channel n
INTDMAn timing is based on DMA execution.
No DMA transfer request pending. This bit is cleared either by start of the DMA transfer or by
writing 0 to the FCLR bit.
DMA transfer request pending.
This bit is set by a DMA request signal input or when writing 1 to the STG bit.
Figure 15-10: DMA Channel Control Register (DMCHCn) Format (1/4)
R
7
0
changing the TCS bit, clear any pending INTDMAn interrupt request flag.
DMCHC0=FFFFFDE0H, DMCHC1=FFFFFDE1H, DMCHC2=FFFFFDE2H,
DMCHC3=FFFFFDE3H, DMCHC4=FFFFFDE4H, DMCHC5=FFFFFDE5H
R
6
0
Chapter 15 DMA Functions (DMA Controller)
TCS
R/W
User’s Manual U16702EE3V2UD00
5
on page 521 for further explanation of the TCS bit and the result-
RQST
R
4
DMA Interrupt Timing Generation
Transfer Request Status Flag
ACF
R
3
FCLR
R/W
2
STG
R/W
1
R/W
EN
0
Address
After reset
00H
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