upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 547

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

16.3.7 Baud rate control function
(1)
(2)
Note: IPT: Information Processing Time
Time segment 1 (TSEG1)
Time segment 2 (TSEG2)
resynchronization Jump
Width (SJW)
Prescaler
The CAN controller has a prescaler that divides the clock (f
generates a CAN protocol layer base clock (f
divided by 1 to 256 (refer to 16.6 (12)”CAN module bit rate prescaler register (CnBRP)” on
page 606).
Data bit time (8 to 25 time quanta)
One data bit time is defined as Figure 16-18. The CAN controller sets time segment 1, time seg-
ment 2, and resynchronization Jump Width (SJW) as the data bit time, as shown in Figure 16-18.
Time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1
that are defined by the CAN protocol specification. Time segment 2 is equivalent to phase seg-
ment 2.
Segment name
Sync segment
User’s Manual U16702EE3V2UD00
Settable range
2TQ to 16TQ
Figure 16-18: Segment Setting
1TQ to 8TQ
1TQ to 4TQ
Prop segment
Chapter 16 FCAN Controller
Time segment 1(TSEG1)
Data bit time(DBT)
TQ
Phase segment 1
IPT
the CAN protocol specification, therefore, a length
equal to phase segment 1 must be set here. This
means that the length of time segment 1 minus 1TQ
is the settable upper limit of time segment 2.
Time segment1-1 TQ length to 4TQ, whichever is
smaller
) that is the CAN module system clock (f
Notes on setting to conform to CAN specification
Note
of the CAN controller is 0TQ. To conform to
Sample point (SPT)
CAN
) supplied to CAN. This prescaler
Phase segment 2
Time segment 2
(TSEG2)
—
CANMOD
547
)