upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 393

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Chapter 11 A/D Converter
11.6.5 Compare match interrupt in timer trigger mode (External trigger mode)
A TMP2 timer P2 capture/compare registers 0, 1 (TP2CCR0, TP2CCR1) underflow interrupt
(INTTP2CC1 or INTTP2CC0) is an A/D conversion start trigger that starts conversion operation. At this
time, the TP2CCR0 or TP2CCR1 match interrupt (INTTP2CC1 or INTTP2CC0) also functions as a
compare register match interrupt for the CPU.
In order not to generate these match interrupts for the CPU, disable interrupts using the mask bits
(TP2CCMK1,TP2CCMK0) of the interrupt control registers (IMR1 or TP2CCIC1 and TP2CCIC0).
11.6.6 Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter
conflict, the A/D conversion value may be undefined. Because of this, be sure to read the A/D
conversion result while the A/D converter is in operation mode.
Furthermore, when reading an A/D conversion result after the A/D converter operation has been
stopped, be sure to have it stop after the time of the next conversion result is complete.
The conversion result read timing is shown in Figures 11-14 and 11-15 below.
Figure 11-14: Conversion Result Read Timing (when Conversion Result is undefined)
A/D conversion end
A/D conversion end
ADA0CRn
Normal conversion result
Undefined value
INTAD
CE bit of ADSCM0H
Undefined
A/D operation
Normal conversion
value read
stopped
result read
Remark:
n = 0 to 15
User’s Manual U16702EE3V2UD00
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