upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 484

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

When the transmission/reception counter reaches the value set by SFN[3:0], then CSOT is cleared “0”
and the transmission/reception end interrupt signal INTC3nI is generated.
After the interrupt occurred, the received data can be read from SIRB. The Read FIFO pointer is auto-
matically incremented by the SIRB read operation.
All FIFO pointers must be cleared by setting FPCLR = 1 before the next transmit/receive cycle can start.
SFP[3:0] represents the [SIO Load/Store FIFO pointer] and shows the number of transmission/recep-
tions completed. In case of SFP[3:0]=0H, the numbers of transmissions/receptions depends on the set-
ting of the SFEMP bit:
SFEMP=0: 0 transmissions/receptions completed
SFEMP=1: 16 transmissions/receptions completed
484
CTXE or CRXE
SFN3-0 Write
SFP3-0 Read
FIFO-counter
FIFO-empty
CS3n[3:0]
INTC3nI
SCK3n
CSOT
SO3n
SI3n
Figure 14-20: FIFO Buffer Transfer Mode (Master, Transmit/Receive) Timing
SIO
0H
0 1
3H
0 1 2
data 0(T)
data 0(R)
CS 0
Transmission
start with
FIFO ready
Chapter 14 Queued CSI (CSI30, CSI31)
data 1(R)
1H
data 1(T)
CS 1
1
User’s Manual U16702EE3V2UD00
data 2(T)
data 2(R)
2H
CS 2
0
Transmission
start with
FIFO ready
3H
0H
4H
data 3(R)
data 3(T)
0 1
CS 3
1H
Initialization with
CTXE or CRXE = 0
0
data 4(T)
data 4(R)
CS 4
2H