upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 407

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

12.3 Control Registers
(1)
Caution:
Remark:
UAnCTL0 UAnPWR UAnTXE UAnRXE UAnDIR UAnPS1 UAnPS0 UAnCL UAnSL
The UAnPWR bit controls the operating clock and asynchronously resets UARTAn. When this bit is cleared to 0,
the output of the TXDAn pin is fixed to the high level for UAnTDL=0 or low level for UAnTDL=1.
When the UAnTXE bit is cleared to 0, the output of the TXDAn pin is fixed to the high level for UAnTDL=0 or low
level for UAnTDL=1.
This bit is synchronized with the operating clock. When the transmission unit is initialized, therefore, set the
UAnTXE bit from 0 to 1. The transmission operation will be enabled two clocks later.
A value written to the UAnTXE bit is ignored when the UAnPWR bit = 0.
When the UAnRXE bit is cleared to 0, the reception operation is stopped. Consequently, even if specified data is
transferred, the reception complete interrupt is not output, and the UAnRX register is not updated.
The UAnRXE bit is synchronized with the operating clock. When the reception unit is initialized, therefore, set the
UAnRXE bit from 0 to 1. The reception operation will be enabled two clocks later.
A value written to the UAnRXE bit is ignored when the UAnPWR bit = 0.
Symbol
UAnPWR
UAnRXE
UAnTXE
UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the serial transfer operation of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 10H.
0
1
0
1
0
1
Address: UA0CTL0: FFFFFA00H, UA1CTL0: FFFFFA10H
Set the UAnPWR bit to 1 and UAnRXE bit to 1 while a high level is being input to the
RXDAn pin (when the UAnRDL bit of the UAnOP0 register is 0). If the UAnPWR and
UAnRXE bits are set to 1 while a low level is being input to the RXDAn pin, reception
is started.
n = 0 to 1
7
Disable clock operation (asynchronously reset UARTAn).
Enable clock operation.
Stop transmission operation.
Enable transmission operation.
Stop reception operation.
Enable reception operation.
Figure 12-2: UARTAn Control Register 0 (UAnCTL0) Format (1/2)
Chapter 12 Asynchronous Serial Interface A (UARTA)
6
User’s Manual U16702EE3V2UD00
5
4
Control of operation of UARTAn
Transmission operation enable
Reception operation enable
3
2
1
0
Address
R/W After Reset
R/W
10H
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