upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 420

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

12.5.4 UART reception
When the UAnPWR bit of the UAnCTL0 register is set to 1 and then the UAnRX bit of the UAnCTL0 reg-
ister is set to 1, UARTA waits for reception. In the reception wait status, the RXDAn pin is monitored and
the start bit is detected.
To recognize the start bit, a two-stage detection routine is used.
When the falling of the RXDAn pin is detected, an 8-bit counter starts counting. When the 8-bit counter
has counted the set value of the UAnCTL2 register, the level of the RXDAn pin is monitored again (indi-
cated by ∇ in Figure 12-13). If the RXDAn pin is low at this time, the start bit is recognized. When the
start bit is recognized, reception is started, and serial data is sequentially stored in the UARTAn receive
shift register at the selected baud rate.
When the stop bit is received, a reception complete interrupt request signal (INTUAnR) is generated
and, at the same time, the data of the UARTAn receive shift register is written to the UAnRX register. If
an overrun error occurs (indicated by the UAnOVE bit of the UAnSTR register), the receive data is not
written to the UAnRX register.
Even if a parity error (indicated by the UAnPE bit of the UAnSTR register) or framing error (indicated by
the UAnFE bit of the UAnSTR register) occurs in the middle of reception, reception continues to the
reception position of the stop bit. The INTUAnR signal is generated when reception is completed.
Cautions: 1. Be sure to read the UAnRX register even when a reception error occurs. Unless
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2. It is always assumed that the number of stop bits is 1 during reception. A second
3. When reception is completed, read the UAnRX register after the reception com-
INTUAnR
UAnRX
the UAnRX register is read, an overrun error occurs when the next data is
received, and the reception error status persists.
stop bit is ignored.
plete interrupt (INTUAnR) has been generated and before clearing the UAnPWR or
UAnRXE bit to 0. If UAnPWR or UAnRXE is cleared to 0 before the interrupt
occurred, the read value of UAnRX is undefined.
Chapter 12 Asynchronous Serial Interface A (UARTA)
Start
bit
D0
Figure 12-13: UART Reception
User’s Manual U16702EE3V2UD00
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit