upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 790

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

25.3 Register Controlling Clock Monitor
The Clock monitor is controlled by the clock monitor mode register (CLM).
(1)
Cautions: 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other
790
Symbol
CLM
R/W
Clock monitor mode register (CLM)
This register is used to set the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
CLME
0
1
2. If reset is occurred for clock monitor, CLME bit is clear (0), and CLMRF bit of
R/W
7
0
than reset.
RESF register is set (1) (see 19.2
page 740).
Disables clock monitor operation
Enables clock monitor operation
Figure 25-2: Clock Monitor Mode Register (CLM) Format
R/W
6
0
R/W
5
0
User’s Manual U16702EE3V2UD00
Chapter 25 Clock Monitor
R/W
Enables/disables clock monitor operation
4
0
R/W
3
0
R/W
2
0
”Registers to Check Reset Source” on
R/W
1
0
CLME
R/W
0
Address
F870H
After reset
00H