upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 538

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

16.2.5 Overload frame
An overload frame is transmitted under the following conditions.
Note: In this CAN controller, all reception frames can be loaded without outputting an overload frame
Remark:
538
<1>
<2>
<3>
<4>
<5>
No
• When the receiving node has not completed the reception operation
• If a dominant level is detected at the first two bits during intermission
• If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit)
of the error delimiter/overload delimiter
because of the high-speed internal processing.
Overload flag
Overload flag from
other node
Overload delimiter
Frame
Interframe space/
overload frame
D: Dominant = 0
R: Recessive = 1
Node n
Name
R
D
(<4>)
¼
node m
Table 16-8: Definition of Overload Frame Fields
Bit Count
6 bits
<1>
0 to 6
6
8
–
–
Overload frame
Figure 16-16: Overload Frame
Chapter 16 FCAN Controller
0 to 6 bits
User’s Manual U16702EE3V2UD00
Outputs 6 dominant-level bits consecutively.
The node that received an overload flag in the interframe space outputs
an overload flag.
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame is trans-
mitted from the next bit.
Output following an end of frame, error delimiter, or overload delimiter.
An interframe space or overload frame starts from here.
<2>
8 bits
<3>
(<5>)
Interframe space or overload frame
Overload delimiter
Overload flag (node n)
Overload flag (node m)
Frame
Definition