upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 327

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

8.5.3 External event counter mode (TQnMD2 to TQnMD0 = 001)
In the external event count mode, the external event count input (TIQn0 pin input) is used as a count-up
signal.
Regardless of the setting of the TQnEEE bit of the TQnCTL0 register, 16-bit timer/event counter Q
counts up the external event count input (TIQn0 pin input) when it is set in the external event count
mode.
In the external event count mode, an interrupt request (INTTQnCC0) is generated when the set value of
the TQnCCR0 register matches the value of the 16-bit counter, and the value of the 16-bit counter is
cleared.
When a value is set to the TQnCCRm register by a write instruction from the CPU, it is transferred to the
CCRm buffer register, and is compared with the value of the 16-bit counter.
In the external event count mode, the 16-bit counter can be cleared only when its value matches the
value of the CCR0 buffer register.
The 16-bit counter cannot be cleared by using the TQnCCRk register.
However, the set value of the TQnCCRk register is transferred to the CCRk buffer register and is
compared with the value of the 16-bit counter. As a result, an interrupt request (INTTQnCCk) is
generated.
By setting the TQnOEm bit to 1, a signal can be output from the TOQnm pin.
When performing timer output with the TOQnk pin, set the same values to the TQnCCR0 register and
the TQnCCRk register since the 16-bit counter cannot be cleared with the CCRk buffer register.
Rewriting the TQnCCR0 register is enabled when TQnCE = 1. When the TQnCCRk register is not
used, it is recommended to set TQnCCRk to FFFFH.
Remark:
n = 0 to 1,
m = 0 to 3
k = 1 to 3
Chapter 8 16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
327