upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 446

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

13.7.4 Continuous mode (master mode, reception mode)
Figure 13-12 shows the transfer timing when data is transferred with the MSB first (CBnDIR bit of
CBnCTL0 register = 0), when continuous transfer mode (CBnTMS bit of CBnCTL0 register = 1), when
the CBnCKP bit of the CBnCTL1 register = 0, when the CBnDAP bit of the CBnCTL1 register = 1, and
when the transfer data length is 8 bits (CBnCL3 to CBnCL0 bits of the CBnCTL2 register = 0, 0, 0, 0).
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
To transfer more data, repeat (5) and (6) before (7).
446
Clear the CBnPWR bit of the CBnCTL0 register.
Specify the transfer mode by setting the CBnCTL1 and CBnCTL2 registers.
Specify the transfer mode by using the CBnDIR bit of the CBnCTL0 register and, at the same time,
enable reception by setting the CBnRXE bit of the CBnCTL0 register to 1.
Enable CSIB operating clock supply by setting the CBnPWR bit of the CBnCTL0 register to 1.
Read dummy data from the CBnRX register (reception start trigger).
The reception complete interrupt request signal (INTCBnR) is generated to inform the CPU that
the CBnRX (CBnRXL) register can be read. Read the CBnRX register before the next receive data
arrives or before the CBnPWR bit is cleared to 0.
Prepare the last receive data by clearing the CBnSCE bit of the CBnCTL0 register to 0.
Confirm that the CBnTSF bit of the CBnSTR register = 0, and stop clock supply to CSIB by clear-
ing the CBnPWR bit to 0 (end of reception).
CBnSCE
CBnTSF
INTCnR
register
Figure 13-12: Continuous Transfer Timing (Master Mode, Reception Mode)
SCKBn
CBnRX
SIBn
Shift
(1) - (4)
(5)
0
Chapter 13 3-Wire Serial Interface (CSIB)
1
0
User’s Manual U16702EE3V2UD00
1
0
1
0
1
(6)
55H
1
(7)
0
55H
1
0
1
0
1
0
(6)
AAH
AAH
(8)
00H
00H