upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 467

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Caution:
Caution:
Caution:
Caution:
See section 14.3.2 ”Serial Data Direction Select Function” on page 477 for further details on
the DIR bit setting.
In combination:
See section 14.3.10 ”Additional Timing and Delay Selections” on page 486 for further details
on the timing selections by CSIT, CSWE, CSMD bits.
CSWE
CSWE
CSMD
CSIT
Figure 14-2: Queued CSI Operation Mode Registers (CSIM0, CSIM1) Format (2/2)
DIR
0
0
1
1
0
1
0
1
0
1
0
1
Write is permitted only when CTXE = 0 and CRXE = 0.
Write is permitted only when CTXE = 0 and CRXE = 0.
This bit is only valid in master mode. In slave mode, no delay is generated.
Write is permitted only when CTXE = 0 and CRXE = 0.
This bit is only valid in master mode. In slave mode, no wait is generated.
Write is permitted only when CTXE = 0 and CRXE= 0.
This bit is only valid for CSWE=1.
This bit is only valid in master mode. In slave mode, CS signals are always held at
inactive level.
Data is sent/received with MSB first
Data is sent/received with LSB first
No delay
Half clock delay
Transmission wait disable. Not insert 1 clock (SCK3) wait at transmission start.
Transmission wait enable. Insert 1 clock (SCK3) wait at transmission start.
Chip select inactive level output disable. Do not force chip select inactive state after each
transfer of a data element.
Chip select inactive level output enable. Hold all chip selects inactive for halt-length SCK3
after each transfer of a data element.
CSMD
0
1
0
1
None
None
One SCK3 length clock wait
One SCK3 length clock wait
Chapter 14 Queued CSI (CSI30, CSI31)
User’s Manual U16702EE3V2UD00
Transmission wait
Interrupt delay mode select (INTC3nI signal)
Transmission wait enable/disable select
Serial data direction selection
Chip Select mode select
Not output
Not output
Not output
Output inactive level of half-length SCK3
during first half of transmission wait
Chip Select inactive level
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