upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 704

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

17.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to
IMR3 registers is equivalent to the xxMKn bit of the xxICn register.
The IMRm register can be read or written in 16-bit units (m = 0 to 3).
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an
IMRmL register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3).
Caution:
Remark:
Note: Be sure to set bit to 1. If these bits are cleared to 0, the operation cannot be
704
IMR3
IMR2
IMR1
IMR0
guaranteed.
After reset: FFFFH
After reset: FFFFH
After reset: FFFFH
After reset: FFFFH
TQ1CCMK0 TQ1OVMK
TP0CCMK0 TP0OVMK TQ0CCMK3 TQ0CCMK2 TQ0CCMK1 TQ0CCMK0 TQ0OVMK
C1RECMK C1WUPMK C1ERRMK
C0TRXMK C0RECMK C0WUPMK C0ERRMK
TP3OVMK TP2CCMK1 TP2CCMK0 TP2OVMK TP1CCMK1 TP1CCMK0 TP1OVMK TP0CCMK1
The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit
is manipulated using the name of xxMKn, the contents of the xxICn register, instead
of the IMRm register, are rewritten (as a result, the contents of the IMRm register are
also rewritten).
UA0RMK
xx:Identification name of each peripheral unit (Refer to Table 17-2, “Interrupt Control Reg-
ister (xxICn),” on page 702)
n:Peripheral unit number (Refer to Table 17-2, “Interrupt Control Register (xxICn),” on
page 700)
xxMKn
PMK6
1
Figure 17-11: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) Format
Note
15
15
15
15
7
7
7
7
0
1
Chapter 17 Interrupt/Exception Processing Function
DMAMK5
Interrupt servicing enabled
Interrupt servicing disabled
CB1TMK
PMK5
14
14
14
14
6
6
6
6
DMAMK4
CB1RMK
PMK4
User’s Manual U16702EE3V2UD00
1
R/W
R/W
R/W
R/W
Note
13
13
13
13
5
5
5
5
DMAMK3
CB0TMK
PMK3
1
1
Note
Note
12
12
12
12
4
4
4
4
Interrupt mask flag setting
DMAMK2
CB0RMK
C31OMK
ADMK
PMK2
1
Note
11
11
11
11
3
3
3
3
Address: FFFF106H
Address: FFFF104H
Address: FFFF102H
Address: FFFF100H
TQ1CCMK3 TQ1CCMK2 TQ1CCMK1
TM0EQMK TP3CCMK1 TP3CCMK0
DMAMK1
UA1TMK
C31MK
PMK1
10
10
10
10
2
2
2
2
DMAMK0
C30OMK
UA1RMK
PMK0
9
1
9
1
9
1
9
1
C1TRXMK
UA0TMK
C30MK
LVIMK
PMK7
8
0
8
0
8
0
8
0