upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 792

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(2)
(3)
792
Figure 25-4: Operation in Software STOP Mode or After Software STOP Mode Is Released
Ring-OSC clock
CPU operation
Operation in software STOP mode or after software STOP mode is released
If the software STOP mode is set with the CLME bit = 1, the monitor operation is stopped in the
software STOP mode and while the oscillation stabilization time is being counted. After the oscilla-
tion stabilization time, the monitor operation is automatically started.
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP
mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time.
Monitoring is stopped in STOP mode and during the oscillation stabilization time.
Operation while CPU is operating on Ring-OSC clock (CCLSF bit of CCLS register = 1)
The monitor operation is not started when the CCLSF bit is 1, even if the CLME bit is set to 1.
CLM status
Main clock
CLM
operation
Normal
Monitoring
Oscillation
Software
STOP
stops
User’s Manual U16702EE3V2UD00
Chapter 25 Clock Monitor
Monitoring stopped
Oscillation stabilization time
Oscillation stabilization time
(set by OSTS register)
Normal operation
Monitoring