upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 500

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(10) FIFO Buffer Transfer Mode (Slave Mode, Transmit Only Mode)
1.
2.
3.
4.
5.
6.
7.
8.
9.
500
CSIB
SCK3 (input)
SFDB write
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 1, DAP = 1, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CTXE bit to 1 to enable transmission.
Set the number of send-data items in the SFN register's SFN[3:0] bits.
Make sure that the SFA register's SFFUL bit is set to 0, then write transmission data in the SFDB
register. (In the slave mode, there is no need to set data in the SFCS register, as the chip select
pins CS3n[3:0] are not used.)
Wait for the transmissions to be completed (e.g. by monitoring the INT3C3nI interrupt).
Write “1” in the SFA register's FPCLR bit and clear all FIFO pointers for the next transmission.
To continue transmission, repeat steps (5) - (8).
Set the CSIM register's CTXE bit to 0 to disable transmission (end of transmission).
CSIBUF_0
CSIBUF_1
CSIBUF_2
CS3n[3:0]
UF-empty
INTC3nI
SFN3-0
SFP3-0
CSOT
CTXE
SO3
(1)
(2)(3)
Figure 14-34: FIFO Buffer Transfer Mode (Slave, Transmit Only) Timing
"inactive level"
(4)
0H
(5)
(6)
3H
0
55H
1
0
(6)
Chapter 14 Queued CSI (CSI30, CSI31)
1
0
AAH
1
User’s Manual U16702EE3V2UD00
0
1
1H
1
0
Wait insertion
by CSIBUF-empty
1
0
1
0
1
0
2H
(6)
1 1
CCH
0 0
1 1
0 0
(7)
3H
(8)
(9)
0H