upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 685

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

Reset
Non-
maskable
Non-
maskable
Software
exception
Software
exception
Excep-
tion trap
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
Maskable Interrupt
The V850E/RS1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can
process a total of 69 interrupt requests.
An interrupt is an event that occurs independently of program execution, and an exception is an event
whose occurrence is dependent on program execution.
The V850E/RS1 can process interrupt requests from the on-chip peripheral hardware and external
sources. Moreover, exception processing can be started by the TRAP instruction (software exception)
or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap).
17.1 Features
•
•
Interrupt/exception sources are listed in Table 17-1.
Type
Interrupts
Non-maskable interrupts:
Maskable interrupts:
8 levels of programmable priorities (maskable interrupts)
Multiple interrupt control according to priority
Masks can be specified for each maskable interrupt request.
Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
Exceptions
Software exceptions:
Exception trap:
Interrupt
Interrupt
Interrupt
Exception
Exception
Exception
Classifica-
tion
Chapter 17 Interrupt/Exception Processing Function
Default
Priority
0
1
2
3
4
5
-
-
-
-
-
-
RESET
INTWDT2
NMI2
TRAP0n
TRAP1n
ILGOP/
DBG0
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
Table 17-1: Interrupt/Exception Source List (1/3)
Name
User’s Manual U16702EE3V2UD00
RESET pin input or Internal
RESET
WDT2 overflow
NMI pin valid edge input
TRAP instruction
TRAP instruction
Illegal open code/
DBTRAP instruction
Low voltage Indicator interrupt
INTP0 pin valid edge input
INTP1 pin valid edge input
INTP2 pin valid edge input
INTP3 pin valid edge input
INTP4 pin valid edge input
Trigger
2 sources
External: 8, Internal: 59 sources
32 sources
2 sources (illegal opcode exception)
Generating
RESET
WDT2
PORT
POCLVI
PORT
PORT
PORT
PORT
PORT
Unit
-
-
-
Exception
00C0H 000000C0H nextPC PIC3
00D0H 000000D0H nextPC PIC4
0000H
0020H
0030H
004nH
005nH
0060H
0080H
0090H
00A0H 000000A0H nextPC PIC1
00B0H 000000B0H nextPC PIC2
Code
00000000H undef.
00000020H nextPC
00000030H nextPC
00000040H nextPC
00000050H nextPC
00000060H nextPC
00000080H nextPC LVIIC
00000090H nextPC PIC0
Address
Handler
Restored
PC
Interrupt
Register
Control
-
-
-
-
-
-
685