upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 25

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

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NP Flag Format ........................................................................................................ 692
NMI Mode Register (NMIM) Format ......................................................................... 693
Maskable Interrupt Servicing ..................................................................................... 695
RETI Instruction Processing ..................................................................................... 696
Example of Processing in Which Another Interrupt Request Is Issued
While an Interrupt Is Being Serviced (1/2)................................................................. 698
Example of Servicing Interrupt Requests Simultaneously Generated....................... 700
Interrupt Control Register (xxICn) Format ................................................................ 701
Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) Format .......................................... 704
In-Service Priority Register (ISPR) Format ............................................................... 705
Maskable Interrupt Status Flag Format .................................................................... 706
Watchdog Timer Mode Register 2 (WDTM2) Format ............................................... 707
External Interrupt Falling Edge Specification Register 0 (INTF0) Format ................ 709
External Interrupt Rising Edge Specification Register 0 (INTR0) Format ................. 709
External Interrupt Falling Edge Specification Register 1 (INTF1) Format ................ 710
External Interrupt Rising Edge Specification Register 1 (INTR1) Format ................. 710
External Interrupt Falling Edge Specification Register 3 (INTF3) Format ................ 711
External Interrupt Rising Edge Specification Register 3 (INTR3) Format ................. 711
External Interrupt Falling Edge Specification Register 9H (INTF9H) Format ........... 712
External Interrupt Rising Edge Specification Register 9H (INTR9H) Format ........... 712
Noise Elimination Control Register Format .............................................................. 713
Software Exception Processing ................................................................................ 714
RETI Instruction Processing ..................................................................................... 715
Exception Status Flag (EP) Format .......................................................................... 716
Illegal Opcode Definition ........................................................................................... 717
Exception Trap Processing ....................................................................................... 718
Restore Processing from Exception Trap.................................................................. 718
Debug Trap Processing Format ............................................................................... 719
Processing Format of Restoration from Debug Trap ................................................ 720
Pipeline Operation at Interrupt Request Acknowledgement (Outline) ....................... 721
Status Transition ....................................................................................................... 724
Standby Transition from PLL Operation (PLL = ON)................................................. 725
Standby Transition from X1 Through Mode (PLL = ON) ........................................... 725
Standby Transition from X1 Through Mode (PLL = OFF) ......................................... 726
IDLE Mode Timing..................................................................................................... 733
Oscillation Stabilization Time .................................................................................... 736
Power Save Control Register (PSC) Format ............................................................ 737
Power Save Mode Register (PSMR) Format ............................................................ 738
Reset Source Flag Register (RESF) Format ............................................................ 740
Timing of Reset Operation by RESET Pin Input ....................................................... 742
Timing of Reset Operation by WDT2RES Signal Generation ................................... 744
Timing of Reset Operation by Low-Voltage Detector ................................................ 746
Regulator Block Diagram .......................................................................................... 747
REGC Pin Connection (REGC = Capacity)............................................................... 748
Address Assignment of Flash Blocks for V850E/RS1 ............................................... 751
Environment Required for Writing Programs to Flash Memory ................................. 752
Communication with Dedicated Flash Programmer (UARTA0)................................. 753
Communication with Dedicated Flash Programmer (CSIB0) .................................... 754
Communication with Dedicated Flash Programmer (CSIB0 + HS) ........................... 754
FLMD0 Pin Connection Example .............................................................................. 756
FLMD1 Pin Connection Example .............................................................................. 757
Signal Conflict (Input Pin of Serial Interface)............................................................. 758
Abnormal Operation of Other Device ........................................................................ 759
Signal Conflict (RESET Pin) ...................................................................................... 760
Recommended Circuit Example ................................................................................ 761
Procedure for Manipulating Flash Memory................................................................ 762
Flash Memory Programming Mode ........................................................................... 763
Timing of Power-on Reset Operation ....................................................................... 742
User’s Manual U16702EE3V2UD00
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