upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 311

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
TQ0CTL0 TQ0CE
TQ1CTL0 TQ1CE
8.4 Control Registers
(1)
Caution:
Remark:
Symbol
Symbol
The TQnCE bit controls the internal operating clock and asynchronously resets TMQn. When this bit is
cleared to 0, the internal operating clock of TMQn is stopped (fixed to the low level), and TMQn is
asynchronously reset.
When the TQnCE bit is set to 1, the internal operating clock is enabled within 2 input clocks, and TMQn
counts up.
Timer Q0 control register 0 (TQnCTL0)
Timer Q0 control register 0 is an 8-bit register that controls the operation of timer Q.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
The same value can always be written to the TQnCTL0 register by software.
TQnCE
TQnCKS2
0
1
<7>
<7>
0
0
0
0
1
1
1
1
Set bits TQnCKS2 to TQnCKS0 when TQnCE = 0.
When the value of the TQnCE bit is changed from 0 to 1, bits TQnCKS2 to TQnCKS0
can be set simultaneously.
n = 0, 1
Disable internal operating clock operation (asynchronously reset TMQn).
Enable internal operating clock operation.
Figure 8-7: Timer Qn Control Register 0 (TQnCTL0) Format
6
0
6
0
TQnCKS1
0
0
1
1
0
0
1
1
5
0
5
0
Chapter 8 16-Bit Timer/Event Counter Q
User’s Manual U16702EE3V2UD00
4
0
4
0
TQnCKS0
0
1
0
1
0
1
0
1
3
0
3
0
Timer Qn operation control
TQ0CKS2 TQ0CKS1 TQ0CKS0 FFFFF540H R/W 00H
TQ1CKS2 TQ1CKS1 TQ1CKS0 FFFFF610H R/W 00H
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
2
2
/2
/4
/8
/16
/32
/64
/128
Internal count clock selection
1
1
0
0
Address
Address
R/W
R/W
After
reset
After
reset
311

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