upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 249

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upd70f3402

Manufacturer Part Number
upd70f3402
Description
32-/16-bit Single-chip Microcontroller With Can Interface
Manufacturer
Renesas Electronics Corporation.
Datasheet
(6)
Caution:
Symbol
OCKS1
R/W
OCKSEN1
OCKSTH1
Clock selection register 1 (OCKS1)
This is an 8-bit register that controls the operation enable and clock input selection for PLL1.
OCKS11
0
1
0
1
0
0
1
1
R
When PLL mode operation is enabled, OCKS1 register value must not be changed.
7
0
PLL1 operation Disable
PLL1 operation Enable
Output clock is divided clock by setting OCKS11 & OCKS10
Output clock is through
OCKS10
R
6
0
Figure 6-15: Clock Selection Register 1 (OCKS1) Format
0
1
0
1
R
5
0
User’s Manual U16702EE3V2UD00
OCKSEN1 OCKSTH1
Chapter 6 Clock Generator
R/W
4
Specified for output clock through or divide
Specified for execution enable
R/W
3
Specified for divider factor
R
2
0
OCKS11 OCKS10 FFFFF864H
f
f
f
f
X
X
X
X
/2
/3
/4
/5
R/W
1
R/W
0
Address
After reset
10H
249

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