upd70f3402 Renesas Electronics Corporation., upd70f3402 Datasheet - Page 493

• Manufacturer Part Number: upd70f3402
• Description: 32-/16-bit Single-chip Microcontroller With Can Interface
• Manufacturer: Renesas Electronics Corporation.

(3)
1.
2.
3.
4.
5.
6.
7.
CSIB
CTXE, CRXE
SFDB write
CSIBUF_1
CSIBUF_2
CSIBUF_0
Single Buffer Transfer Mode (Master Mode, Transmit/Receive Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 1, DAP = 0, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to “active low”:
SIRB read
Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
Set the CSIC and CSIL registers to specify the transfer mode.
Write “1” in the SFA register's FPCLR bit to clear all FIFO pointers.
Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CTXE and CRXE bits to 1 to enable the transmit/receive operation.
Make sure that the SFA register's SFFUL bit is set to 0, then write chip-select data and
transmission data in the SFCS and SFDB registers in this order.
Check for a transmission to be finished (e.g. by monitoring the INTC3nI interrupt). If so, read the
SIRB register.
Repeat steps (5) and (6) until the last element is send/received and read from the SIRB register.
Set the CSIM register's CTXE and CRXE bits to 0 to disable the transmit/receive operation (end of
transmit/receive operation).
UF-empty
CS3n[3:0]
INTC3nI
SFP3-0
SCK3
CSOT
SIRB
SO3
Figure 14-27: Single Buffer Transfer Mode (Master, Transmit/Receive) Timing
(1)
SI3
(2)(3)
"active-L"
0
(4)
(5)
1
0
1
55H
1
1
0
0
(5)
Chapter 14 Queued CSI (CSI30, CSI31)
0
User’s Manual U16702EE3V2UD00
1
2
CS 0
0
1 1
Wait insertion by SIRB-full before
INTC3nI/SIRB store/CSTO clear
1
AAH
0
0 0
1
1
1
1
CCH
0
0 0
1
CS 1
0
1
1
0
0
1 1
1
0
0
(6)
0
Wait insertion
by CSIBUF-empty
96H
(5)
1
33H
1
0
0
0 0
1
(6)
1
1 1
CS 2
0
0
0 0
1 1
1
0
(6)
(7)
99H
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